01 / SECURE FLOOR
Secure engineering floorDesign, checks and the evidence ledger run on your machines. In air-gapped mode, outbound traffic stops at the boundary.OpenCE Lab · AI for the physical world
Engineering intelligence into matter.
We build the AI that designs circuit boards and programs them. Layer turns a sentence into a board a factory can build. Core turns that board into firmware that has been run and proved on real hardware.
BOARD100 × 70 mm · 8 layers
ROUTING0 / 0 nets
PROCESSORBGA · 0.8 mm pitch
MEMORY2 × LPDDR4 · eMMC · QSPI NOR
Software learned to write itself. Hardware is still drawn by hand, one trace at a time, by a few people who know how. We are changing who gets to build physical things.
01 — DESIGNA sentence becomes a board.Requirements, architecture, real parts, schematic, placement, routing and fabrication files, each step checked before the next one starts.
02 — PROGRAMA board becomes a working device.Core reads the schematic, writes firmware from the datasheets, builds it, flashes it with your approval and watches it run.
03 — PROVEEvery claim carries its evidence.Design-rule checks, electrical checks, measurements on the bench. Unknown is never shown as a pass. You sign every step that matters.
Physical AI
AI can think.
It cannot yet build.
Models write code, read papers and reason about physics. We are closing the gap between that and the physical world.
01Models can reason about hardware.
They read datasheets, follow electrical rules and reason about physics. That was not true a few years ago.
02Hardware is the bottleneck.
Between an AI and the world sits a board and its firmware. That step is still slow, manual and expert-only.
03The world needs more of it.
Robots, edge devices and instruments need boards and firmware at a scale people alone cannot draw.
We are building the toolchain for physical AI.
Core writes, builds and flashes firmware for the silicon you already useCHIP PACKS · BOARD PACKS · ZEPHYR · PLATFORMIO · ESP-IDF · ARDUINO
STMicroelectronics
Espressif
Nordic Semiconductor
Raspberry Pi
Arduino
RENESAS
Silicon Labs
Analog Devices
Seeed Studio
PJRC Teensy
NVIDIA Jetson
BeagleBoard
STMicroelectronicsEspressifNordic SemiconductorRaspberry PiArduinoRENESAS
Silicon Labs
Analog Devices
Seeed Studio
PJRC Teensy
NVIDIA Jetson
BeagleBoard
Two products · one project
The board, and the code that runs on it.
Each works on its own. Together they share one project, from the first sentence to a device that has been proved on the bench.
Product 01 · AI PCB design→
Layer
Describe the board in plain words. Layer turns it into requirements, real parts, a schematic, a routed board and files a factory can build.
BriefPartsSchematicRoutingChecksFab files
Product 02 · AI firmware engineering→
Core
Upload the schematic and say what the device should do. Core writes the firmware from the datasheets, flashes it with your approval and proves it works.
MissionDatasheetsBuildFlashLiveVerdict
Inside the products
What Layer and Core actually do, step by step.
No black box. Each product runs a fixed sequence of steps, and each step leaves something you can open, check and keep.
LayerSentence → manufacturable board
Reads your brief
Turns plain words into numbered, testable requirements, with assumptions and the questions it cannot answer alone.
→ brief.md · REQ-01…Plans the architecture
Blocks, power tree, interfaces and budgets, every value tied to a datasheet page, calculation or requirement.
→ architectureChooses real parts
Live stock, price breaks and lifecycle. Verified symbols, footprints and 3D models. Alternates ranked.
→ BOM + alternatesDraws the schematic
Hierarchical sheets in native KiCad format, with electrical rule checks on every save.
→ .kicad_schPlaces and routes
Parts grouped by function, decoupling at every supply pin, copper routed around anything you locked.
→ .kicad_pcbChecks everything
Design rules judged by KiCad, electrical rules, manufacturability, power and signal analysis.
→ gate reportHands you the files
Gerber, drill, BOM, pick-and-place, IPC-2581, STEP, a review pack and a bring-up plan.
→ release.zipCoreSchematic → proven firmware
Imports your board
Reads the processor, pins, buses and parts from a KiCad or Altium project and builds a board target.
→ board targetReads the datasheets
Registers, timing and errata from your document library, cited by page. Asks you to confirm what it relies on.
→ document libraryPlans with you
Proposes the steps and the assumptions. Nothing is written, built or flashed until you approve.
→ approved planWrites the firmware
Drivers and application code, each line tied back to a requirement.
→ src/Builds locally
ESP-IDF, Zephyr, PlatformIO or Arduino, on your machine. Warnings are treated as findings.
→ firmware imageFlashes with approval
ST-LINK, J-Link, CMSIS-DAP, esptool or DFU. Every flash is hash-verified and logged.
→ flash recordObserves and judges
Serial, telemetry, scopes and camera, compared against the requirements, with a verdict.
→ PASS + evidenceEvidence on every claimEach answer cites the datasheet page, rule or check behind it. Anything unsourced is marked unverified.Principle
Approvals are signaturesNothing reaches the copper or the chip without a person approving it.Principle
Unknown is never greenPass, fail, partial or not run. Colours tell the truth about every check.Principle
Your files, open formatsNative KiCad, Gerber, IPC-2581, STEP, Markdown and JSON. No lock-in, ever.Layer
Hand edits are sacredCopper you route by hand is never touched. Your edits become fixed points.Layer
Honest costAn estimate before every AI run, caps you control, and no charge for runs that fail.Layer · Core
Evidence on every claimEach answer cites the datasheet page, rule or check behind it. Anything unsourced is marked unverified.Principle
Approvals are signaturesNothing reaches the copper or the chip without a person approving it.Principle
Unknown is never greenPass, fail, partial or not run. Colours tell the truth about every check.Principle
Your files, open formatsNative KiCad, Gerber, IPC-2581, STEP, Markdown and JSON. No lock-in, ever.Layer
Hand edits are sacredCopper you route by hand is never touched. Your edits become fixed points.Layer
Honest costAn estimate before every AI run, caps you control, and no charge for runs that fail.Layer · Core
Grounded in datasheetsCore reads the register map before it writes a single line of driver code.Core
Safe robotics bring-upHard limits listed before every motor test, with a live E-STOP the whole time.Core
Local by defaultProjects, checks, logs and keys stay on your machines. Air-gapped when you need it.Platform
Any model, your keysOpenAI, Anthropic, Gemini, Azure or a local model, through your own contracts.Platform
Bench proves itA design is not done when it compiles. It is done when the board does what you asked.Principle
Never trained on youYour designs, code and recordings are never used to train models.Platform
Grounded in datasheetsCore reads the register map before it writes a single line of driver code.Core
Safe robotics bring-upHard limits listed before every motor test, with a live E-STOP the whole time.Core
Local by defaultProjects, checks, logs and keys stay on your machines. Air-gapped when you need it.Platform
Any model, your keysOpenAI, Anthropic, Gemini, Azure or a local model, through your own contracts.Platform
Bench proves itA design is not done when it compiles. It is done when the board does what you asked.Principle
Never trained on youYour designs, code and recordings are never used to train models.Platform
How it works
From a sentence to a device that works.
Four moves, one project. Every step that touches copper or a chip waits for your approval.
01DescribeWrite what the product must do. Layer turns it into testable requirements.
02DesignParts, schematic, placement and routing, each gated by a check.
03ProgramCore imports the board, writes the firmware and flashes it after you approve.
04ProveMeasured on the bench, compared with the requirements, with a verdict.
OpenCE Lab
A lab for the physical AI era.
OpenCE is a lab. We build the tools that let intelligence leave the screen and become things: boards, devices, robots and instruments. Layer and Core are the first two. More are being built in the lab now.
AVAILABLE
Layer
AI PCB design. From a written brief to a checked board and fabrication files.AVAILABLE
Core
AI firmware engineering. From a schematic to firmware proved on the bench.IN DEVELOPMENTDense boardsFour- to eight-layer routing, BGA escape, length-matched memory buses and controlled impedance.
PROTOTYPEPhysics in the loopPower, signal and thermal simulation that steers placement and routing, not only checks them afterwards.
RESEARCHHardware-in-the-loop benchesAutomated test rigs that measure every revision and feed the results back into the design.
RESEARCHRobots that bring themselves upActuators found, characterised and tuned inside hard safety limits, from a description of the machine.
Items marked in development, prototype or research are directions of work in the lab, not products you can buy today.
For every builder
EnterpriseAir-gapped, audited, approved.On your machines, with your model contracts and a full audit trail.Enterprise →
InstitutionsOne semester, one real device.Lab licences, instructor review and course libraries for universities and labs.Institutions →
PricingFrom $10per seat per month. Buy Layer and Core together and save up to 13%.See pricing →
Product 01 · AI PCB design
Layer
Describe what the board must do. Layer writes the requirements, chooses real parts with stock and datasheets, draws the schematic, places and routes the copper, runs the checks and hands you files a factory can build. Watch it work below: the board is routed in your browser as you scroll.
Illustration. A simplified router running live in this page routes the board. Layer routes 2-layer boards end to end today. 4–8 layers are on the roadmap.
0/0nets routed
0vias
0 mmcopper length
—clearance check
BRIEFRequirements you can testA sentence becomes numbered requirements with assumptions and open questions. Freeze them, and every later decision is traced back to one.
ARCHITECTUREBlocks, power tree, budgetsEvery value carries its source: datasheet page, calculation or requirement. Layer suggests alternatives. You add or dismiss them.
PARTSReal parts, in stockLive stock, price breaks and lifecycle from distributors. Verified symbols, footprints and 3D models. Every datasheet claim cited to its page.
SCHEMATICA real schematic, not a pictureHierarchical sheets in native KiCad format. Electrical rule checks run on save, with each finding tied to the rule and the part.
PCBPlacement and routingParts grouped by function, decoupling at every supply pin, routing that respects your locked copper. Long jobs stream their best result as they go.
REVIEWProposals, never surprisesEvery AI change arrives as a ghost on your board. Checks run on it before you see it. You accept item by item, and every acceptance is recorded.
PHYSICSAnalysis on the real copperPower delivery, voltage drop, signal integrity, thermal and creepage on the geometry that was just routed, with the run saved so anyone can reproduce it.
3DFit before fabricationComponents, heights and enclosure in three dimensions. A missing model is drawn as a stand-in and named, never silently guessed.
OUTPUTSFiles that belong to youNative KiCad project, Gerber, drill, pick-and-place, BOM, IPC-2581, STEP, a review pack and a bring-up plan. No lock-in.
Checks, not promises
The AI proposes. The checks decide. You sign.
Every stage of Layer ends at a gate: a deterministic check that passes, fails or is honestly partial. A failing hard gate blocks the next step. There is no button to waive it.
PASSDesign rulesClearance, drill, annular ring, courtyard and silk, judged by KiCad itself.
PASSElectrical rulesUndriven power pins, floating inputs and dangling labels, with sheet and part named.
PASSManufacturabilityChecked against the fab profile you choose, before you upload anything.
PARTIALRouting completePartial routing is shown as partial. It is a result, not something to hide.
PASSPower deliveryImpedance against target, decoupling placement and plane splits.
PASSSignal integrityImpedance, length and skew matching, crosstalk and return paths.
PASSOutputs re-readFabrication files read back by independent tools and compared with the design.
NOT RUNRelease approvalNeeds a person who did not make the design. Grey until then, never green.
Product 02 · AI firmware engineering
Core
Upload the schematic and describe what the device should do. Core's AI engineer reads the datasheets, plans, writes the code, builds it, flashes it only after you approve, watches it run and tells you whether it works. This is the real Core workflow, replayed.
MissionLiveHardwareRoboticsFleet & Proof
LIVE BOARD
Target —
Probe none
Agent idle
ACTIVITY
AGENT ACTIONS
0 of 50 used
SERIAL › —clangd readyKeys in OS keychain · audit log on
MISSIONSay what it should doDescribe the behaviour in plain words. Choose Learn to explore, Build to approve each step, or Autopilot to run inside an action budget you set.
HARDWARESchematic in, target outImport a KiCad or Altium project and its parts list. Core reads the processor, pins and buses and builds a board target with build, flash, debug and verify.
DOCUMENTSGrounded in datasheetsDatasheets, errata and app notes in one library. The agent cites them by page and asks you to confirm the facts it relies on.
TOOLCHAINSBuild and flash for realESP-IDF, Zephyr, PlatformIO and Arduino. esptool, CMSIS-DAP, DFU, ST-LINK and J-Link. Every flash is approved, hash-verified and logged.
LIVESee what the device doesSerial monitor, telemetry channels, scopes, camera and recordings in one workbench, replayed next to the code that produced them.
ROBOTICSMotors inside limits you setFind actuators on the bus, characterise them and tune them with hard limits listed up front, and a live E-STOP the whole time.
LINUX BOARDSFrom card to first bootRaspberry Pi, BeagleBone, Jetson and more. Write the OS, boot, install the agent, stream sensors. You approve every step that changes something.
FLEET & PROOFTests across devicesRun the same checks on many boards. Requirements, code, tests and bench results stay linked, so every line of firmware has a reason.
MODELSAny model, your keysOpenAI, Anthropic, Gemini, Azure or a local model. Keys stay in the system keychain. Air-gapped mode allows local models only.
Workflow
One project, from a sentence to a device that works.
Layer and Core share the same project. The board Layer designs is the board Core programs. What the bench teaches comes back to the board as a proposal for the next revision.
LAYERDescribeWrite what the product must do. Layer turns it into requirements and asks what it cannot assume.
LAYERDesignArchitecture, parts, schematic, placement and routing, with an approval at each gate.
LAYERManufactureChecks against your fab, then fabrication and assembly files with a review pack.
COREProgramImport the same project. Plan, code and build from the datasheets. Flash after you approve.
COREProveObserve on the bench, compare with the requirements and give a verdict with its evidence.
What it unlocks
A new economy of things.
When designing a device costs what building an app costs, the long tail of hardware gets built. Robots, sensors and tools that no large company would ever make, made by the people who need them.
RoboticsMotor drivers, power stages and sensor-fusion boards, brought up inside safe limits with a live E-STOP.
Edge AI devicesCameras, gateways and smart sensors that run models where the data is, on boards designed for them.
New productsFrom prototype to manufacturable design in weeks, with evidence that investors and factories can read.
IndustryIsolated I/O, fieldbus nodes and monitoring hardware for factories, energy, water and agriculture.
Research instrumentsLab equipment and measurement rigs designed by the scientists who need the measurement.
EducationEvery student designs, orders and programs a real board in one semester, and can explain each decision.
Deployment
Everything stays inside your boundary.
Workstations, lab benches, the local engine and the model endpoint all live on your network. In air-gapped mode the public internet is simply not an option.
Where it fits
Where OpenCE fits in your programme.
From the secure floor where boards are designed, to the line that builds them, to the devices in the field. One record follows the hardware the whole way.
02 / DESIGN TO LINE
From design to lineThe release package your line receives is the one your reviewer signed. Open formats, no conversion step to trust.03 / REGULATED DEVICE
Regulated deviceEach check, approval and flash is tied to the exact board and build it touched. Export it when the auditor asks.04 / FLEET PROOF
Fleet proofKnow which firmware and which evidence went onto every unit you flashed. Partial results are shown as partial, never rounded up.All four panels are illustrations of how OpenCE is meant to be used. They are not photos of customer sites or real devices.
Security & control
Controls your security team will ask for.
Plain answers, not marketing. What ships today is marked as such. What is on the roadmap is marked too.
DATAProjects stay localDesign files, checks and the evidence ledger live on your disks and in your version control.
MODELSYour contractsOpenAI, Anthropic, Azure AI Foundry, Gemini or a private endpoint. Keys stay in the OS keychain.
NETWORKAir-gapped modeOnly local model endpoints are allowed and outbound connections are refused.
AUDITAppend-only ledgerEvery agent call, gate result, approval and flash, with hashes. Exportable for review.
HARDWAREPeople approve hardware actionsFlashing, writes to buses and motor tests open a native approval. Agents cannot approve.
ROADMAPSSO and central policySingle sign-on, role-based policy and fleet-wide caps are planned and will be marked when they ship.
Governance
Release is a signature, not a button.
A design moves forward only when its checks pass and a named reviewer, who is not the author, signs it.
01AuthorAn engineer, or the AI on their behalf, proposes a change.
02ChecksDeterministic gates run. A failing hard gate blocks progress.
03ReviewerA different person reviews the proposal and its evidence.
04ReleaseFrozen, hashed and recorded. Nothing moves without sign-off.
Medical devicesAerospace & defenceAutomotive suppliersIndustrial automationEnergy & utilitiesRoboticsTest & measurement
How we start
From first call to rollout.
STEP 1ScopingYour programme, your boards, your constraints and your compliance needs.
STEP 2PilotLayer and Core on your machines, on a real project, with your libraries.
STEP 3Security reviewYour team inspects deployment, data flows and the audit trail.
STEP 4RolloutTraining, custom rules and packs, and dedicated support.
Institutions · Education & research
Teach hardware by building it.
Hardware is taught with simulators and kits because real boards were too slow and too costly to put in every student's hands. With Layer and Core, every student designs, orders, programs and defends a real device in a single term.
A term, end to end
One semester. One real device.
A course plan that fits a standard term. Students finish with a board they designed, firmware they can explain, and a record of every decision.
WEEKS 1–2BriefStudents write what their device must do. Layer turns it into testable requirements.Layer
WEEKS 3–5Architecture & partsBlocks, power budgets and real parts with stock and datasheets.Layer
WEEKS 6–8Schematic & layoutA real KiCad schematic and a routed board, every step checked.Layer
WEEK 9Fab orderManufacturing files go to a class panel at an approved fab.Layer
WEEKS 10–12FirmwareCore imports the board and writes firmware from the datasheets.Core
WEEKS 13–14Bench & reviewThe device is flashed, measured and defended in a design review.Core
In their hands
What a student works with.
Not a simulator. A board they designed, a probe to debug it, and a brief to build against. By the end of term it works, or they know exactly why it doesn't.
ILLUSTRATION · TYPICAL COURSE KIT
- 1Their own boardDesigned by the student in Layer, checked against the course rules and fabricated through the class panel order.
- 2USB-C cablePower and data. Plug in and Core finds the board.
- 3Sensor breakoutSomething real to measure, chosen by the instructor for the brief.
- 4Debug probeFlash, step and read registers. Core drives it; students see every step.
- 5The briefWhat the device must do, in plain language. Every check traces back to it.
A typical course setup, shown as an illustration. The institution supplies the hardware; instructors choose the parts, the sensor and the brief.
ILLUSTRATION
THE LAB BENCH
Debug on real signals.
Layout on the laptop, the board on the bench, the waveform on the scope. Students learn what a missed timing actually looks like.
ILLUSTRATION
THE CLASS PANEL
One order for the whole class.
Every student's design checked against the same rules, then panelised into one fab order. Snap out your own board.
ILLUSTRATION
CAPSTONE
A device that does something.
A robot, a sensor station, an instrument for a research group. Built on a board the student designed, running firmware they can explain.
Who it is for
UniversitiesElectronics, embedded systems, mechatronics and capstone projects with real boards.
Colleges & polytechnicsHands-on courses where every student ships a working device.
Research labsInstruments and test rigs built by the people who need the measurement.
MakerspacesShared machines, safe defaults and usage caps for open workshops and bootcamps.
For instructors
Grade the thinking, not just the result.
Layer and Core record every decision a student makes and every proposal they accept or reject. Assessment becomes reading the design history.
A
Approvals map onto gradingStudents submit for review; instructors approve, request changes or comment, step by step.
L
The full ledgerEvery check, citation and accepted proposal, so you can see what the student understood.
C
Course librariesApproved parts, fab profiles and rules, so students design inside the limits you set.
$
Caps per studentAI usage budgets per course and per student, set by instructors, never exceeded.
Programme
Three ways to bring it to campus.
Accredited institutions receive programme pricing well below commercial plans. Tell us about your course and cohort, and we will send a proposal.
CourseOne course, one cohort.
- Student seats for Layer and Core
- Instructor seats with review tools
- Per-student usage caps
- Starter curriculum and briefs
DepartmentEvery course in a department.
- Everything in Course
- Shared department libraries
- Approved fab profiles and class panels
- Onboarding for teaching staff
CampusTeaching, research and makerspaces.
- Everything in Department
- Research group seats
- Makerspace machines with safe defaults
- Dedicated support
"The best way to learn hardware has always been to build it. Now every student can."
Apply for the programmePricing
Two products. Priced separately. Better together.
Per seat, per month. AI model usage is billed by your own provider key, with an estimate before every run and caps you control.
Enterprise
For regulated and high-stakes hardware programmes.
Custom
- Layer and Core for your whole team
- Air-gapped deployment with local models
- Audit export, approvals as policy
- Custom libraries, rules and packs
- Onboarding and dedicated support
Institutions
For universities, colleges, research labs and makerspaces.
Custom
- Student and instructor seats, per course or per site
- Usage caps per student, set by instructors
- Course libraries and approved fabs
- Curriculum material and onboarding
- Accredited-institution discount
Model usageBilled by your model provider through your key. Estimates shown before every run.
Free checksDesign rules, electrical rules and manufacturability checks never cost extra on any plan.
Failed runsA run that ends invalid is not charged by us, and is marked that way in the log.
SeatsPer named person. Move a seat to someone else at any time.
Questions
Asked and answered.
How is this different from a chat assistant?+
Layer and Core work on your real design files and your real hardware. They run deterministic checks, cite their sources and present every change as a proposal. Nothing reaches the copper or the chip without your approval.
Can I use Layer or Core on its own?+
Yes. Each works independently. Together they share one project from board to firmware, and the combo plans cost less than buying both.
What can Layer design today?+
Two-layer boards end to end: microcontroller boards, sensors, USB-C power, regulators, motor drivers, CAN and RS-485 nodes, audio and interface boards. Four-layer support is in development. Six- and eight-layer boards with BGA escape follow. Anything beyond the current limit is refused in writing, never silently simplified.
Which boards does Core support?+
ESP32 family, STM32, Nordic nRF, Raspberry Pi RP2040 and RP2350, Teensy, Arduino and Seeed boards, and Linux boards such as Raspberry Pi, BeagleBone, Jetson Orin Nano and i.MX 8M Plus. Custom boards are added by importing their schematic.
Which AI models are supported?+
OpenAI, Anthropic, Google Gemini, Azure AI Foundry and any OpenAI-compatible endpoint, including models running locally. Keys stay in your operating system's keychain.
Where does our data go?+
Nowhere you did not choose. Both apps keep projects locally. Model calls go only to the provider you configured. Your designs are never used for training.
What do we receive at the end?+
From Layer: a native KiCad project with Gerber, drill, pick-and-place, BOM, IPC-2581, STEP, a review pack and a bring-up plan. From Core: firmware that has been built, flashed and run on the target, with a verdict and an audit log.